An SRAM Main Memory Model

A growing gap between CPU and DRAM performance is driving processors further away from their peak execution rates by increasing the amount of time spent waiting for the memory system. To date, cache memories have been used to good e ect in o setting lagging DRAM speeds by bu ering frequently referenced instructions and data near the CPU. However, continued increases in the cost of DRAM accesses call for improvements in cache performance, and in particular, that of the secondary cache. More speci cally, strategies which target the secondary cache hit rate for improvement are becoming increasingly important, even if they result in an increase in the cost of each miss. This research examines a proposed new organization for the memory hierarchy in which main memory is implemented in SRAM (replacing the secondary cache), and the role of DRAM is relegated to that of a paging device. In this model, called the RAMpage memory hierarchy, a software-managed paging system takes the place of the traditional, hardwareimplemented block placement and replacement strategies used by the secondary cache. Effectively, full associativity is provided for in SRAM, and this occurs at no additional cost or cycle time penalties to the hardware. Moreover, treating the secondary cache as main memory facilitates pinning of critical operating system code and data in that level, further reducing the total number of references which reach DRAM. Working against these bene ts, however, is the increase in the cost of an SRAM miss (now called a page fault), which results from the invocation of memory management software to retrieve the missing information from DRAM. Trace-driven simulation is used to evaluate the performance of the RAMpage hierarchy. The results presented in this research indicate a reduction of between 40 and 90% in the total number of references to DRAM, and these are shown to amortize the additional overheads incurred by the paging software required to achieve them. Scalability of the RAMpage hierari chy is also demonstrated through the extent to which an increasing CPU-DRAM gap causes its performance to degrade relative to that of a conventional memory hierarchy. Overall, reductions of between 3 and 17% in total simulation time are achieved by the new hierarchy. While a more detailed analysis of the RAMpage hierarchy is called for, the preliminary simulation results presented here indicate good potential for its overall success. This research therefore demonstrates that the RAMpage hierarchy represents a feasible alternative to conventional organizations of the memory hierarchy, and more importantly, one which will become increasingly attractive as the gap between CPU and DRAM speeds continues to widen. ii Acknowledgements The idea of an SRAM main memory model originates from my supervisor, Philip Machanick. I wish to thank Philip for his assistance throughout this research work, especially for his many useful comments and suggestions, both in the experimental work, and in the preparation of this report. The experimental work would not have been possible without sel ess contributions of John Ostrowick, Roger Ingo Mateer, Sherona Hoosen and Lance Pompe. Thanks to all of you for the provision of, and assistance with, the various hardware platforms on which the simulations were conducted. Amitha Perera also provided numerous helpful comments in the preparation of the simulators. I would also like to thank both my parents for their unending support and encouragement. Thanks especially to my father for his careful proof reading of this report. Finally, thank you Nicole for your moral support and for so much more. iii